1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device. More particularly, the invention relates to a method of fabricating a semiconductor device with a metal or metals (e.g., copper) filled in a recess of a dielectric material. The invention is preferably applicable to fabrication of semiconductor devices having copper-system metal filled in a recess of a dielectric layer formed on or over a substrate or wafer.
2. Description of the Related Art
In conventional semiconductor integrated circuit devices (i.e., Ultralarge-Scale Integrated circuit devices, ULSIs), aluminum (Al) and alloys of Al (i.e., Al-system metals) have been used as the wiring metal, because Al-system metals are low in specific resistance and easy to be patterned. In recent years, however, according to the progressing demand to further increase the integration scale, miniaturization scale, operation speed, and reliability of ULSIs, the use of copper (Cu) and alloys of Cu (i.e., Cu-system metals) as the wiring metal has started and extended. This is because Cu-system metals are lower in resistivity and higher in electromigration (EM) resistance than Al-system metals.
Cu-system metals have a disadvantage that they are difficult to be patterned by dry etching. Therefore, when wiring lines are formed by a Cu-system metal, some contrivance is necessary for the patterning process. One of the contrivances of this sort, which is termed the “damascene process”, is disclosed in the Japanese Examined Patent Publication No.5-46983 published in 1993, which corresponds to the U.S. Pat. No. 4,789,648 issued on Dec. 6, 1988. The “damascene process” is carried out in the following way.
Trenches (or recesses) are formed in the surface of an interlayer dielectric layer to form a wiring pattern and then, a Cu layer is deposited on the whole surface of the interlayer dielectric layer in such a way as to fill the trenches. Subsequently, the overlying part of the Cu layer with respect to the interlayer dielectric layer is selectively removed to expose the surface of the interlayer dielectric layer by the Chemical Mechanical Polishing (CMP) process, thereby selectively leaving the Cu layer in the trenches. This process is termed the “single damascene process” because only the buried wiring lines are formed through this process.
Not only trenches (or recesses) but also via holes may be formed in the surface of an interlayer dielectric layer to form a wiring pattern and via plugs. In this case, a Cu layer is then deposited on the whole surface of the interlayer dielectric layer in such a way as to fill the trenches and the via holes. Subsequently, the overlying part of the Cu layer with respect to the interlayer dielectric layer is selectively removed to expose the surface of the interlayer dielectric layer by the CMP process, thereby selectively leaving the Cu layer in the trenches and the holes. This process is termed the “dual damascene process” because both the buried wiring lines and the via plugs connected to the lines are simultaneously formed through this process. The “dual damascene process” has an advantage that the total number of necessary fabrication processes is decreased and that the fabrication cost is lowered.
To fill a Cu layer into wiring trenches (or wiring trenches and via holes), it is known that the high-temperature reflowing method, sputtering method, or electroplating method may be used. If the wiring trenches have a high aspect ratio, the electroplating method is preferred.
When a metal layer (e.g., a Cu layer) is filled into wiring trenches and via holes by the electroplating method, a seed Cu layer is formed on the inner side and bottom walls of the trenches and the holes in advance. The seed Cu layer is used as a cathode in the electroplating process. Thereafter, a Cu layer is plated in such a way as to fill the trenches and holes.
Recently, however, filling failure or defect of a Cu layer was likely to occur even if the electroplating method was used. This is because the need to reduce the wiring line width has been promoted according to the progressing miniaturization of ULSIs and as a result, the aspect ratio of wiring trenches and via holes has been raised furthermore.
For example, there is the need to fill via holes having an aspect ratio greater than four with a Cu layer. If a seed Cu layer is formed on the inner faces of a high aspect-ratio via hole of this type by the sputtering method, desired, sufficient coverage may not be obtainable. In particular, Cu is deposited on the inner side face of the via hole in such a way as to form islands in the vicinity of the bottom of the hole, resulting in a discontinuous seed Cu layer. In the area that includes the discontinuous seed Cu layer, a Cu layer will grow scarcely or insufficiently by the electroplating method. This is because the electroplating bath for the Cu layer, which is a mixture of CuSO4.5H2O and H2SO4, is strong acid and therefore, the dissolving rate of the discontinuous (i.e., island-shaped) seed Cu layer is larger than the growth rate of the Cu layer by plating. Accordingly, during the electroplating process, Cu grows sufficiently in the area where the seed Cu layer is continuous and at the same time, Cu grows scarcely or insufficiently in the remaining area where the seed Cu layer is discontinuous. This means that the via hole is unable to be filled with the Cu layer, resulting in unwanted voids in the hole.
To compensate the lack of the seed Cu layer, the thickness of the seed Cu layer may be increased. In this case, however, there arises a disadvantage that the seed Cu layer will be formed in such as way as to overhang outstandingly near the top of the via hole, thereby closing the top of the hole before the hole is filled with the Cu layer. This phenomenon is termed “pinch off” of the hole. If “pinch off” occurs, a large void or voids will be formed in the hole. As a result, the thickness of the seed Cu layer is unable to be increased as desired to compensate the lack of the seed Cu layer.
One of the measures or improvements to solve the above-identified problem is disclosed in the Japanese Non-Examined Patent Publication No. 2000-183160 published in Jun. 30, 2000. In this improvement, after a seed Cu layer (which is discontinuous or island-shaped) is formed, a reinforcing Cu layer is formed on the seed Cu layer by the electroless plating method, thereby eliminating the discontinuity of the seed Cu layer. Thereafter, a Cu layer is formed on the reinforcing Cu layer by the electroplating method in such a way as to fill the hole.
With the improvement disclosed in the Publication No. 2000-183160, however, there are the following disadvantages. Specifically, another plating bath is needed for the electroless plating process, which makes the plating apparatus highly complicated. Moreover, it is known that the popular electroless plating method is less in stability, reproducibility, and mass-productivity.
Another measure or improvement to solve the above-identified problem is to use the long-throw sputtering method or the ionized sputtering method. With the long-throw sputtering method, the distance between the substrate and the sputtering target is increased compared with the popular sputtering method. On the other hand, with the ionized sputtering method, sputtered Cu atoms are ionized and at the same time, a bias voltage is applied to the substrate, thereby actively introducing the ionized Cu atoms into the inside of the hole.
With the said improvement, however, the substrate temperature is raised by bombardment of the sputtered atoms or ions with the substrate and as a result, there is a disadvantage that agglomeration of the Cu layer is likely to occur.
Generally, a seed Cu layer is formed on a barrier metal layer in such a way that the energy of the seed Cu layer itself is minimized. Therefore, if a sufficient energy (e.g., due to high temperature) is applied to the seed Cu layer to cause “surface migration” of Cu atoms, agglomeration of the Cu layer will occur.
FIG. 1A is a photograph showing the state of agglomeration of the seed Cu layer in a via hole of a dielectric layer. This photograph was obtained by the inventor's test where a seed Cu layer was formed under the condition that the holder temperature was set at 80° C. As seen from FIG. 1A, the seed Cu layer was discontinuously is treated as one lot. Therefore, usually, semiconductor wafers in one lot are transferred into the process chamber of a deposition apparatus (e.g., a sputtering apparatus) and then, seed Cu layers are formed on the respective wafers in the lot. The inside of the chamber is kept in a vacuum during the deposition process. Subsequently, the wafers in the lot are transferred from the chamber of the deposition apparatus into the atmosphere and thereafter, transferred to a plating apparatus for a desired plating process. Thus, the earlier-deposited wafers in the lot are kept in the vacuum at room temperature until deposition for a seed Cu layer is completed for the remaining wafers in the same lot. Since the earlier-deposited wafers are not cooled during the waiting or holding period, the seed Cu layer is likely to be agglomerated due to “surface migration”. This problem (i.e., the post-deposition agglomeration) can be overcome by cooling the earlier-deposited wafers during the waiting period. However, this measure makes it necessary to provide an additional cooling system, raising the fabrication cost of the semiconductor device. Thus, this measure is not preferred.
According to the inventor's test, the post-deposition agglomeration of a seed Cu layer is prominently observed in an area where the seed Cu layer is thin (e.g., the inner side face of a via hole with a high aspect ratio). When a Cu layer was formed by plating on the seed Cu layer where the post-deposition agglomeration had occurred, similar filling failure or defect to FIG. 1B was observed.